mosel vitelic 1 v62c21164096 256k x 16, 0.20 m cmos static ram preliminary v62c21164096 rev. 1.6 october 2001 features high-speed: 70, 85 ns ultra low cmos standby current of 4a (max.) fully static operation all inputs and outputs directly ttl compatible three state outputs ultra low data retention current (v cc =1.2v) operating voltage: 2.3v ? 3.0v packages ? 44-pin tsop (standard) ? 48-ball csp bga (8mm x 10mm) description the v62c21164096 is a 4,194,304-bit static random-access memory organized as 262,144 words by 16 bits. inputs and three-state outputs are ttl compatible and allow for direct interfacing with common system bus structures. device usage chart operating temperature range package outline access time (ns) power temperature mark tb7085lll 0 cto70 c blank ?40 cto+85 c i functional block diagram row decoder 1024 x 4096 memory array input data circuit column i/o column decoder control circuit v cc gnd a 0 a 8 a 9 a 7 a 6 i/o 1 i/o 16 lbe oe we ube a 10 a 17 ce 1 ce 2
2 v62c21164096 rev. 1.6 october 2001 mosel vitelic v62c21164096 pin descriptions a 0 ?a 17 address inputs these 18 address inputs select one of the 256k x 16 bit segments in the ram. ce 1 ,ce 2 * chip enable inputs ce 1 is active low and ce 2 is active high. both chip enables must be active to read from or write to the device. if either chip enable is not active, the device is deselected and is in a standby power mode. the i/o pins will be in the high-impedance state when deselected. oe output enable input the output enable input is active low. with chip enabled, when oe is low and we high, data will be presented on the i/o pins. the i/o pins will be in the high impedance state when oe is high. ube ,lbe byte enable active low inputs. these inputs are used to enable the upper or lower data byte. we write enable input the write enable input is active low and controls read and write operations. with the chip enabled, when we is high and oe is low, output data will be present at the i/o pins; when we is low and oe is high, the data present on the i/o pins will be written into the selected memory locations. i/o 1 ?i/o 16 data input and data output ports these 16 bidirectional ports are used to read data from and write data into the ram. v cc power supply gnd ground pin configurations (top view) 44-pin tsop-ii (standard) 48 bga a4 a3 a2 a1 a0 ce 1 i/o1 i/o2 i/o3 i/o4 vcc gnd i/o5 i/o6 i/o7 i/o8 we a15 a14 a13 a12 a16 a5 a6 a7 oe ube lbe i/o16 i/o15 i/o14 i/o13 gnd vcc i/o12 i/o11 i/o10 i/o9 nc a8 a9 a10 a11 a17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 a 123456 1 note: nc means no connect. 23456 b c d e f g h top view top view a ble i/o9 i/o10 b c d e f g h vss vcc i/o15 i/o16 nc oe bhe i/o11 i/o12 i/o13 i/o14 nc a8 a0 a3 a5 a17 nc a14 a12 a9 a1 a4 a6 a7 a16 a15 a13 a10 a2 ce 1 i/o2 i/o4 i/o5 i/o6 we a11 ce 2 i/o1 i/o3 vcc vss i/o7 i/o8 nc *ce 2 is available on bga package only.
mosel vitelic v62c21164096 3 v62c21164096 rev. 1.6 october 2001 part number information absolute maximum ratings (1) note: 1. stresses greater than those listed under ? absolute maximum ratings ? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. symbol parameter commercial industrial units v cc supply voltage -0.5 to v cc + 0.5 -0.5 to v cc +0.5 v v n input voltage -0.5 to v cc + 0.5 -0.5 to v cc +0.5 v v dq input/output voltage applied v cc +0.3 v cc +0.3 v t bias temperature under bias -10 to +125 -65 to +135 c t stg storage temperature -55 to +125 -65 to +150 c sram family c = cmos process 62 = standard 21 = 2.3v ? 3.0v operating voltage 4096k organization pkg speed 62 c 16 21 4096 ? mosel-vitelic manufactured v 16 = 16-bit 70 ns 85 ns temp. blank = 0 c to 70 c i = -40 c to +85 c t = tsop standard b = bga density pwr. l = low power ll = double low power capacitance* t a =25 c, f = 1.0mhz note: 1. this parameter is guaranteed and not tested. symbol parameter conditions max. unit c in input capacitance v in =0v 6 pf c out output capacitance v i/o =0v 8 pf truth table note: x=don ? t care, l = low, h = high mode ce 1 ce 2 oe we ube lbe i/o 9-16 operation i/o 1-8 operation standby h x x x x x high z high z standby x l x x x x high z high z output disable l h x x h h high z high z output disable l h h h x x high z high z read l h l h l l d out d out read l h l h l h d out high z read l h l h h l high z d out write l h x l l l d in d in write l h x l l h d in high z write l h x l h l high z d in
4 v62c21164096 rev. 1.6 october 2001 mosel vitelic v62c21164096 dc electrical characteristics (over all temperature ranges, v cc =2.3v ? 3.0v) notes: 1. these are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 2. v il (min.) = -3.0v for pulse width < 20ns. 3. maximum values. symbol parameter test conditions min. typ. max. units v il input low voltage (1,2) -0.3 ? 0.4 v v ih input high voltage (1) 2.0 ? v cc +0.3 v i il input leakage current v cc =max,v in =0vtov cc -1 ? 1 a i ol output leakage current v cc =max,ce =v ih ,v out =0vtov cc -1 ? 1 a v ol output low voltage v cc =min,i ol =2.1ma ?? 0.4 v v oh output high voltage v cc =min,i oh = -0.5ma v cc ? 0.4 ?? v symbol parameter power com. (3) ind. (3) units i cc1 average operating current, ce 1 =v il ,ce 2 =vcc ? 0.2v, output open, v cc =max. f = fmax 35 40 ma f=1mhz 4 5 i sb ttl standby current ce v ih ,v cc =max.,f=0 l0.51ma ll 0.3 1 i sb1 cmos standby current, ce 1 v cc ? 0.2v, ce 2 <0.2v v in v cc ? 0.2v or v in 0.2v, v cc =max.,f=0 l1015 a ll 4 6 ac test conditions ac test loads and waveforms key to switching waveforms input pulse levels 0 to 2.0v input rise and fall times 5 ns timing reference levels 1.1v output load see below * includes scope and jig capacitance c l * ttl c l = 30 pf + 1 ttl load waveform inputs outputs must be steady will be steady may change from h to l will be changing from h to l may change from l to h will be changing from l to h don't care: any change permitted changing: s tat e unknown does not apply center line is high impedance ? off ? s tat e
mosel vitelic v62c21164096 5 v62c21164096 rev. 1.6 october 2001 data retention characteristics notes: 1. t rc =readcycletime 2. t a =+25 c. low v cc data retention waveform (ce controlled) symbol parameter power min. typ. (2) max. units v dr v cc for data retention ce 1 v cc ? 0.2v, ce 2 <0.2v,v in v cc ? 0.2v, or v in 0.2v 1.2 ? 3.0 v i ccdr data retention current ce 1 v dr ? 0.2v, ce 2 <0.2v,v in v cc ? 0.2v, or v in 0.2v, v dr =1.2v com ? ll ? 13 a ll ? 0.5 2 ind. l ?? 5 ll ?? 4 t cdr chip deselect to data retention time 0 ?? ns t r operation recovery time (see retention waveform) t rc (1) ?? ns v cc data retention mode ce 1 v cc ? 0.2v ce 1 2.0v 2.0v 2.3v t cdr t r v dr 1.2v 2.3v
6 v62c21164096 rev. 1.6 october 2001 mosel vitelic v62c21164096 ac electrical characteristics (over all temperature ranges) read cycle write cycle parameter name parameter 70 85 unit min. max. min. max. t rc read cycle time 70 ? 85 ? ns t aa address access time ? 70 ? 85 ns t acs chip enable access time ? 70 ? 85 ns t ba ube ,lbe access time ? 70 ? 85 ns t oe output enable to output valid ? 35 ? 35 ns t clz chip enable to output in low z 10 ? 10 ? ns t blz ube ,lbe to output in low z 10 ? 10 ? ns t olz output enable to output in low z 5 ? 10 ? ns t chz chipdisabletooutputinhighz 0 25 0 30 ns t ohz output disable to output in high z 0 25 0 30 ns t bhz ube ,lbe to output in high z 0 25 0 30 ns t oh output hold from address change 5 ? 10 ? ns parameter name parameter 70 85 unit min. max. min. max. t wc write cycle time 70 ? 85 ? ns t cw chip enable to end of write 60 ? 70 ? ns t as address setup time 0 ? 0 ? ns t aw address valid to end of write 60 ? 70 ? ns t wp write pulse width 50 ? 60 ? ns t wr write recovery time 0 ? 0 ? ns t whz write to output high-z 0 20 0 25 ns t dw datasetuptoendofwrite 35 ? 40 ? ns t dh data hold from end of write 0 ? 0 ? ns t bw ube ,lbe to end of write 60 ? 70 ? ns
mosel vitelic v62c21164096 7 v62c21164096 rev. 1.6 october 2001 switching waveforms (read cycle) read cycle 1 (1,2,7) read cycle 2 (1,2,4,6,7) read cycle 3 (1,3,4,6,7) notes: 1. we =v ih . 2. ce 1 =v il .ce 2 =v ih . 3. address valid prior to or coincident with ce transition low. 4. oe =v il . 5. transition is measured 500mv from steady state with c l = 5pf. this parameter is guaranteed and not 100% tested. 6. ube =v il ,lbe =v il . 7. ce 2 isofferedonbgapackageonly. address oe i/o ube, lbe t rc t aa t oe t bhz t olz t blz t ba t ohz (5) address i/o t rc t aa t oh t oh address i/o ce 1 t acs t clz (5) t chz (5) ce 2
8 v62c21164096 rev. 1.6 october 2001 mosel vitelic v62c21164096 switching waveforms (write cycle) writecycle1(we controlled) (4, 7) writecycle2(cecontrolled) (4, 7) notes: 1. the internal write time of the memory is defined by the overlap of ce 1 and ce 2 active and we low. all signals must be active to initiate and any one signal can terminate a write by going inactive. the data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 2. t wr is measured from the earlier of ce 1 or we going high, or ce 2 going low at the end of the write cycle. 3. during this period, i/o pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 4. oe =v il or v ih . however it is recommended to keep oe at v ih during write cycle to avoid bus contention. 5. if ce 1 is low and ce 2 is high during this period, i/o pins are in the output state. then the data input signals of opposite phase to the outputs must not be applied to them. 6. t cw is measured from ce 1 going low or ce 2 goinghightotheendofwrite. 7. ce 2 is available on bga package only. address output input ce 1 ce 2 we t wc t cw (6) t cw (6) t dw t dh t aw t wr (2) t whz t wp (1) t as address output high-z input ce 1 ce 2 we t wc t dw t dh t aw t cw (6) t cw (6) t wr (2) t as (4) (5)
mosel vitelic v62c21164096 9 v62c21164096 rev. 1.6 october 2001 package diagrams 44-pin 400 mil tsop-ii 48 ball ? 8x10 bga 0.741[18.81] max 0.725 0.004 [18.41 0.10] 0.031 [0.80] 0.032 [0.80] 0.004 max 44 23 122 0.047 [1.20] max unit in inches [mm] 0.400 [10.16] 0.463 0.008 [11.76 0.20] 0.014 0.004 [0.35 0.10] 0.000 [0.0] min +0.004 -0.002 0 ? 5 0.020 0.006 [0.50 .019] 0.006 +0.01 -0.05 0.15 e1 e 6 5 4 d abcde bottom view side view aaa fg h d1 b solder ball 3 2 1 e a c a1 symbol a a1 b c d d1 e e1 e aaa unit.mm 1.05+0.15 0.25 0.05 0.35 .0.05 0.30(typ) 10.00 0.10 5.25 8.00 0.10 3.75 0.75typ 0.10
mosel vitelic worldwide offices v62c21164096 mosel vitelic 3910 n. first street, san jose, ca 95134-1501 ph: (408) 433-6000 fax: (408) 433-0952 tlx: 371-9461 ? copyright , mosel vitelic inc. printed in u.s.a. the information in this document is subject to change without notice. mosel vitelic makes no commitment to update or keep cur- rent the information contained in this document. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of mosel-vitelic. mosel vitelic subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applica- tions. mosel vitelic does not do testing appropriate to provide 100% product quality assurance and does not assume any liabil- ity for consequential or incidental arising from any use of its prod- ucts. if such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications. u.s. sales offices u.s.a. 3910 north first street san jose, ca 95134 phone: 408-433-6000 fax: 408-433-0952 taiwan 7f, no. 102 min-chuan e. road, sec. 3 taipei phone: 886-2-2545-1213 fax: 886-2-2545-1209 no 19 li hsin road science based ind. park hsin chu, taiwan, r.o.c. phone: 886-3-579-5888 fax: 886-3-566-5888 singapore 10 anson road #23-13 international plaza singapore 079903 phone: 65-3231801 fax: 65-3237013 japan onze 1852 building 6f 2-14-6 shintomi, chuo-ku tokyo 104-0041 phone: 03-3537-1400 fax: 03-3537-1402 uk & ireland suite 50, grovewood business centre strathclyde business park bellshill, lanarkshire, scotland, ml4 3nq phone: 44-1698-748515 fax: 44-1698-748516 germany (continental europe & israel) benzstrasse 32 71083 herrenberg germany phone: +49 7032 2796-0 fax: +49 7032 2796 22 northwestern 3910 north first street san jose, ca 95134 phone: 408-433-6000 fax: 408-433-0952 southwestern 302 n. el camino real #200 san clemente, ca 92672 phone: 949-361-7873 fax: 949-361-7807 central, northeastern & southeastern 604 fieldwood circle richardson, tx 75081 phone: 214-352-3775 fax: 214-904-9029
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